1. Technical Field
This present invention relates to a level shifter and, more specifically, to a level shifter with higher operating speed and larger voltage converting range.
2. Description of Related Art
With the advancements made in semi-conductor process technology, different process generations can be selected and adopted to different electronic circuits, according to various requirements, in order to reach optimization in operating speed, circuit size, power consumption and hardware costs. For example, signal processors, for which high operating speeds and low power consumption are required, can be realized by deep sub-micron process. Thus, central processing unit (CPU) is realized by 22-nanometer semi-conductor process. When higher output voltage or output power is required in an application, such as loud-speaker driver circuits and motor driver circuits, the semi-conductor process, of which the devices can endure higher voltage, can be properly adopted.
However, on the processing on digital signals propagated among different circuit modules, care must be taken when transmitting and receiving digital signals with proper voltage levels to maintain normal operation of the electronic circuits. For example, a voltage source of 1-volt or lower will be required for the aforementioned deep sub-micron process; however, a 1.8-volt, 3.3-volt, or 5-volt voltage is required for a semi-conductor process of other applications. When different circuits of different operating voltages are adopted in the same application, the level shifter is indispensable for normal circuit operation. For example, a level shifter is required to convert the voltage level of a digital signal from a core circuit to output onto other application circuits, and vice versa. The general principles on the design of the level shifter are high speed, small size, large voltage converting range, and maintenance of duty cycle of the input signals.
FIG. 1 is a circuit diagram of a level shifter 100 of prior art. Transistors 101 and 102 form an input stage circuit, which receives a first input signal and a second input signal, wherein the second input signal is out-of-phase to the first input signal. The first input signal is a digital logic signal received by an input terminal 110, and the second input signal is a digital logic signal generated by an inverter 120 which receives the first input signal as an input. A voltage level of the second input signal is determined by a voltage on an input reference voltage terminal 130 coupled by the inverter 120. Transistor 103 and 104 form a latch circuit, which is coupled to the input stage circuit through a first output terminal 105 and a second output terminal 106. The latch circuit and the input stage circuit determine the steady-state levels of the first output terminal 105 and the second output terminal 106 according to the first input signal and the second input terminal. The latch circuit also forms a positive feedback changing the states of the first output terminal 105 and the second output terminal 106 during transient operation. A voltage level of the voltages on the first output terminal 105 and the second output terminal 106 are determined by a voltage on an output reference voltage terminal 140. Besides, the level shifter 100 further includes an inverter 150, of which the input terminal is coupled to the second output terminal 106 and the output terminal of the inverter 150 is the output terminal 160 of the level shifter 100. The inverter 150 may not only enhance the output driving ability of the level shifter 100 but also adjust the duty cycle of the output signal.
FIG. 2 is a timing diagram of a level shifter according to the level shifter 100. Waveforms 210, 220, 230, 240 and 250 correspond to the voltage waveforms of first input signal, the second input signal, the first output terminal 105, the second output terminal 106 and the output terminal 160 respectively. Before time instant t1, the first input signal and the second input signal are logic levels “0” and “1” respectively, which are shown by waveforms 210 and 220. At time instant t1, a positive edge is triggered on the input terminal 110, the first input signal is changed from digital logic level “0” to logic level “1”, and inverter 120 correspondingly generates logic level “0” to form the second input signal, which is out-of-phase to the first input signal. Meanwhile, since the first input signal is logic level “1”, a channel of the transistor 101 starts to conduct. Although a channel of the transistor 103 still conducts, because the transistor 101 is designed to be stronger than the transistor 103, a negative edge correspondingly happens on the first output terminal 105, which is shown by the waveform 230. Following at time instant t2, since the voltage on the first output terminal 105 is already low enough to control a channel of the transistor 104 conducting, the second output terminal 106 is charged and a positive edge happens thereon, which is shown by the waveform 240. Then at time instant t3, since the voltage of the second output terminal 106 is high enough, a negative edge happens on the output of the inverter 160, which is shown by the waveform 250.
Further, at time instant t4, a negative edge is triggered on the input terminal 110, the first input signal is changed from logic level “1” to logic level “0”, and correspondingly the second input signal is changed from logic level “0” to logic level “1”. And the channel of the transistor 102 is conducted and triggers a negative edge on the second output terminal 106. After a finite delay time, at the time instant t5, a positive edge correspondingly happens on output terminal 160.
As shown in FIG. 2, a delay time between the input terminal 110 and the output terminal 160 is approximately (t3−t1) when corresponding to a positive edge triggered on the input terminal 110, and is approximately (t5−t4), which is obviously different from (t3−t1) when corresponding to a negative edge triggered on the input terminal 110. There are at least the following disadvantages for the above-mentioned phenomena caused by the level shifter 100 of prior art. First, it takes too long for a positive edge to transit on the first output terminal 105 or the second output terminal 106, which limits the operating speed of the level shifter 100. Second, the duty cycle of the signal on the output terminal 160 cannot be maintained approximately the same as to that of the signal on the input terminal 110. While it can be improved by adjusting the rising and falling slope of the signals related to the inverter 150, the adjusting effect would be limited when the operating voltage, process variation and operating temperature are taken into consideration.
Furthermore, the principle of the level shifter 100 of prior art is that, when the input signal changes the state, the channel of the transistor 101 or 102 is conducted to force a negative edge that occurs on the first output terminal 105 or the second output terminal 106. Meanwhile, the channel of the transistor 103 or 104 is still conducted. Hence, the transistors 101 and 102 are designed to be stronger than the transistors 103 and 104; otherwise, malfunction of the level shifter 100 will occur. However, when a design margin is considered based on operating voltage, process variation and operating temperature, the transistors 103 and 104 would be relatively weak, resulting an even longer positive edge transition on the first output terminal 105 and the second output terminal 106, which cannot be solved due to the intrinsic principle of the level shifter 100. Besides, when the voltage of the output reference voltage terminal 140 becomes higher, the transistors 103 and 104 will get stronger, which is not advantageous to maintain the level shifter 100 functions normally. As a result, the voltage converting range is also limited for the level shifter 100.